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3.1.7.3
Low-Pass Filter Selection Bits (LPF[3:0])
The Low Pass Filter selection bit selects a low-pass filter as shown in Table 11 . Refer to Section 3.8.3 for details regarding
filter configurations.
Table 11. Low Pass Filter Selection Bits
LPF[3]
LPF[2]
LPF[1]
LPF[0]
Low Pass Filter Selected Nominal Sample Rate ( μ s)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100 Hz, 4-pole
300 Hz, 4-Pole
400 Hz, 4-Pole
800 Hz, 4-Pole
1000 Hz, 4-Pole
400 Hz, 3-Pole
Reserved
Reserved
50 Hz, 4-Pole
150 Hz, 4-Pole
200 Hz, 4-Pole
400 Hz, 4-Pole
500 Hz, 4-Pole
200 Hz, 3-Pole
Reserved
Reserved
8
8
8
8
8
8
Reserved
Reserved
16
16
16
16
16
16
Reserved
Reserved
Note: Filter characteristics do not include g-cell frequency response.
3.1.8
Arming Configuration Registers (ARMCFG)
The arming configuration register contains configuration information for the arming function. The values in this register are only
relevant if the arming function is operating in moving average mode, or count mode.
This register can be written during initialization but is locked once the ENDINIT bit is set. Refer to Section 3.1.6.2 . This register
is included in the writable register CRC check. Refer to Section 3.2.2 for details.
Table 12. Arming Configuration Register
Location
Bit
Address
$0E
Register
ARMCFG
7
Reserved
6
Reserved
5
APS[1]
4
APS[0]
3
AWS_N[1]
2
AWS_N[0]
1
AWS_P[1]
0
AWS_P[0]
Reset Value
0
0
0
0
1
1
1
1
3.1.8.1
Reserved Bits (Reserved)
Bits 7 through 6 of the ARMCFG register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device
operation and performance.
MMA685x
Sensors
16
Freescale Semiconductor, Inc.
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